1. Field of the Invention
This invention relates to the field of semiconductor manufacture, and more specifically to the formation of deep trenches when etching silicon.
This invention describes a process for etching multiple films with a dual layer hard mask, and specifically a process for etching deep trenches for DRAMs having a dual layer hard mask. The top hard mask is totally and the lower hard mask is partially removed while etching the deep trench.
2. Description of Related Art
In the formation of integrated circuits, it is often necessary to etch a trench in the silicon substrate. In particular, the trend towards packing more memory cells into a given chip area has led to the development of trench memory cells which require deep, narrow apertures in the silicon substrate. Trench memory cells and trench capacitors with one or more polysilicon electrodes for silicon integrated circuits have applications in structures known as dynamic random access memories (DRAMs).
Deep trench etching of the silicon substrate has many problems during the etching process and in the post-etch processing of the substrate. The side walls of trench cells and trench capacitors must be substantially vertical to minimize the amount of space consumed by the trench. However, the manufacturing sensitivity of the silicon substrate can inhibit control and precision during the etching process. In post-etch processing, hard masks used in patterning the trenches must be removed with minimal undercutting of the pad dielectric on the substrate. In addition, manufacturing costs are driven up when there are multiple masking steps, and seasoning changes in the etch tool.
U.S. Pat. No. 4,717,448 (issued Jan. 5, 1988, to Cox et al. and assigned to the assignee of the present invention), discloses a process for forming deep trenches in a silicon substrate having a layer of silicon oxide, and a photoresist layer. Undercutting of the silicon oxide can occur during deep trench etching of the substrate utilizing this method.
U.S. Pat. No. 4,983,253 (issued Jan. 8, 1991, to Wolfe et al.) discloses an apparatus and method of etching a silicon wafer having a layer of pad oxide wherein two masking layers may be used when etching the silicon. This method requires additional steps to remove the masking layers.
U.S. Pat. No. 5,275,974 (issued Jan. 4, 1994, to Ellul et al.), discloses a method of forming trench capacitor electrodes with reduced masking steps by etching a substrate coated, first, with a layer of silicon nitride as a chemical mechanical polish stop and then coated with a layer of silicon oxide to serve as a trench etch mask. The silicon oxide is removed during post-etch processing and later re-grown.
U.S. Pat. No. 5,470,782 (issued Nov. 28, 1995, to Schwalke et al.), discloses a method for producing trench structures in silicon substrates using a two-stage trench process comprising at least two etching steps utilizing multiple layers of silicon dioxide, mono- and polycrystalline silicon, and silicon nitride. The layers are etched first followed by etching of the silicon substrate. This method involves several time consuming deposition steps.
DRAMs have been manufactured with a borosilicate glass (BSG)/pad nitride hard mask and with a tetraethylorthosilicate (TEOS)/pad nitride hard mask. Following deep trench etch of the TEOS/pad nitride product, the same chamber is often used to run BSG/pad nitride product. The chamber experiences process shifts causing the BSG product to etch deeper, and erode the BSG/pad nitride hard mask. A current solution to this problem is to allow a buildup of BSG products before seasoning the chamber from the TEOS product run. After running the BSG product, the chamber must be reseasoned to prepare the chamber for running TEOS products. Dedicating chambers based on tool, process, or product differences is not a manufacturable solution since it impacts capacity. A more flexible manufacturing solution is desirable.
Bearing in mind the problems and deficiencies of the prior art, it is an object of the present invention to provide a method of deep trench etching silicon having improved control and precision to allow etching trenches of close proximity and/or with multiple dimensions and directions.
Another object of the present invention is to provide a method of deep trench etching silicon having reduced pad oxide undercut.
It is yet another object of the present invention to provide a method of deep trench etching silicon having improved post-etch processing.
A further object of the present invention is to provide a silicon substrate for etching a plurality of trenches within close proximity.
A still further object of the present invention is to provide a silicon substrate for etching a plurality of trenches having multiple dimensions and directions.
Yet another object of the present invention is to provide an improved manufacturing process for deep trench etching of DRAMs.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
The above and other objects and advantages, which will be apparent to one of skill in the art, are achieved in the present invention which is directed to, in a first aspect, a method of etching a plurality of trenches in a semiconductor substrate. The method comprises the steps of: (a) providing a semiconductor substrate capable of being etched with a first etchant, having a layer of pad dielectric disposed thereon; (b) depositing a layer of material capable of selective removability with respect to the pad dielectric; (c) depositing a layer of material having a slower etch rate than the semiconductor substrate and the layer of material capable of selective removability with respect to the pad dielectric when contacted with the first etchant; (d) patterning at least one of the layers to form a pattern for the trench; (e) etching through the layers; and (f) contacting the semiconductor substrate with the first etchant to form the trench and removing the layer of material having a slower etch rate than the semiconductor substrate.
Preferably, in step (b) the layer of material capable of selective removability with respect to the pad dielectric is borosilicate glass (BSG). Preferably, in step (c) the layer of material having a slower etch rate than the semiconductor substrate when contacted with the first etchant is a layer of silicon oxide deposited by plasma enhanced chemical vapor deposition.
Preferably, during step (e) etching of the pad dielectric, the layer of material capable of selective removability with respect to the pad dielectric, and the layer of material having a slower etch rate than the semiconductor substrate, there is no substantial etching of the semiconductor substrate.
Preferably, etching of the silicon substrate comprises reactive ion etching with an etchant comprising hydrogen bromide gas, nitrogen triflouride, with oxygen and helium. Most preferably, during etching of the silicon substrate, the nitrogen triflouride completely removes the layer of silicon oxide.
Preferably, further including in step (f) removing any remaining layer of material capable of selective removability with respect to the pad dielectric, and removing the layer of material having a slower etch rate than the semiconductor substrate when contacted with the first etchant comprising dipping the semiconductor substrate in a hydrogen fluoride-sulfuric acid bath selective to the layer of pad dielectric and the silicon substrate.
A first preferred sequence of the first three steps is: first, providing a semiconductor substrate capable of being etched with a first etchant, having a layer of pad dielectric disposed thereon; followed by depositing a layer of material capable of selective removability with respect to the pad dielectric; then depositing a layer of material having a slower etch rate than the semiconductor substrate and the layer of material capable of selective removability with respect to the pad dielectric when contacted by the first etchant; and followed by steps (d) through (f).
A second preferred sequence of the first three steps is: first, providing a semiconductor substrate capable of being etched with a first etchant, having a layer of pad dielectric disposed thereon; followed by depositing a layer of material having a slower etch rate than the semiconductor substrate when contacted by the first etchant; then depositing a layer of material capable of selective removability with respect to the pad dielectric; and followed by steps (d) through (f).
The second preferred sequence may further include, after step (f) wherein a first trench is formed, the steps of: (g) completely removing the layer of material capable of selective removability with respect to the pad dielectric; (h) filling the first silicon trench; (i) depositing a subsequent layer of material capable of selective removability with respect to the pad dielectric; (j) patterning the layers; and (k) etching a subsequent trench in the semiconductor substrate, wherein the subsequent trench can have a different dimension and direction than the first trench.
In another aspect, the present invention relates to a method of etching trenches of close proximity on a silicon substrate. The method comprising the steps of: (a) providing a silicon substrate capable of being etched with a first etchant; (b) depositing a layer of pad dielectric over the silicon substrate; (c) depositing a layer of BSG over the layer of pad dielectric; (d) depositing a layer of silicon oxide over the layer of BSG; (e) applying a resist layer and exposing the pattern on the layers of silicon oxide, BSG and pad dielectric; (f) etching the layers of silicon oxide, BSG and pad dielectric; (g) stripping the remaining resist layer; and (h) contacting the silicon substrate with first etchant to form the trenches while removing at least a portion of the layer of silicon oxide.
The method of etching trenches of close proximity may further include steps (i) removing any remaining layers of silicon oxide and BSG; and (j) growing a node insulator film within the trenches and filling the trenches with polysilicon.
Preferably, in step (c) the layer of BSG is thicker than the layer of silicon oxide. Preferably, in step (d) the layer of silicon oxide is deposited by plasma enhanced chemical vapor deposition. Preferably, during step (f) etching of the pad dielectric, the layer of material capable of selective removability with respect to pad dielectric, and the layer of material having a slower etch rate than the semiconductor substrate, there is no substantial etching of the semiconductor substrate.
During step (h) wherein the silicon substrate is contacted with the first etchant to form the trenches while removing at least a portion of the layer of silicon oxide, the layer of silicon oxide protects the layer of BSG during etching of the silicon substrate. The rate of erosion of the layer of BSG is reduced and the rate of etching of the silicon substrate is better controlled than with a layer of BSG alone.
In yet another aspect, the present invention relates to a method of etching a plurality of trenches having different dimensions and directions in a silicon substrate. The method comprises the steps of: (a) providing a silicon substrate capable of being etched with a first etchant, having a layer of pad dielectric over the silicon substrate, a first layer of silicon oxide deposited over the layer of pad dielectric by plasma enhanced chemical vapor deposition, a layer of BSG deposited over the first layer of silicon oxide; (b) etching the layers of pad dielectric, silicon oxide and BSG in accordance with a desired pattern; (c) contacting the silicon substrate with the first etchant to produce the plurality of trenches in the silicon substrate; and (d) removing the layer of BSG with an etchant selective to the first layer of silicon oxide to provide a planar surface on the first layer of silicon oxide after removing the layer of BSG. According to the present method the first layer of silicon oxide and the layer of BSG are of substantially equal thicknesses.
Wherein step (c) forms a first plurality of trenches, the present aspect further includes the steps of: (e) growing a first layer of node insulator onto the walls of the trenches then filling the first plurality of trenches with polysilicon; and (f) removing any excess polysilicon and node insulator forming a planar surface on the first layer of silicon oxide. The step of removing any excess polysilicon and node insulator comprises chemical mechanical polishing of the excess polysilicon to achieve a surface planar to the layer of silicon oxide.
The etching of subsequent trenches further includes the steps of: (g) depositing a subsequent layer of silicon oxide, preferably, having a thickness of about 2000 xc3x85 to about 4000 xc3x85, over the first layer of silicon oxide by plasma enhanced chemical vapor deposition; (h) etching through the first and subsequent layers of silicon oxide, and the layer of pad dielectric; (i) etching subsequent silicon trenches; (j) removing the first and subsequent layers of silicon oxide; (k) growing a subsequent layer of node insulator onto the walls of the subsequent trenches and filling the subsequent trenches with polysilicon; and (l) removing any excess polysilicon and node insulator down to the layer of pad dielectric. The subsequent trenches etched can have different dimensions and directions than the first plurality of silicon trenches.
Preferably, in step (l) the removal of any excess polysilicon and node insulator comprises chemical mechanical polishing to achieve a surface planar to the layer of pad dielectric.
In still yet another aspect, the present invention relates to an intermediate silicon substrate for use in deep trench etching comprising: a silicon substrate; a layer of pad dielectric disposed on the silicon substrate; a layer of BSG disposed on the layer of pad dielectric; a layer of silicon oxide disposed on the layer of BSG by plasma enhanced chemical vapor deposition; and a resist layer disposed on the layer of silicon oxide, wherein the layer of silicon oxide provides a sacrificial layer protecting the layer of BSG to minimize moisture sensitivity of the layer of BSG during deep trench etching of the silicon substrate. The intermediate silicon substrate is for use in etching a plurality of trenches within close proximity.
In still yet another aspect, the present invention relates to an intermediate silicon substrate for use in deep trench etching comprising: a silicon substrate; a layer of pad dielectric disposed on the silicon substrate; a layer of silicon oxide disposed on the layer of pad dielectric by plasma enhanced chemical vapor deposition; a layer of BSG disposed on the layer of silicon oxide; and a resist layer. The intermediate silicon substrate is for use in deep trench etching a plurality of trenches of same or differing dimensions and directions.